EP1S40F1020C7N

Product Summary

The EP1S40F1020C7N is an FPGA, which contains a two-dimensional row and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks. The EP1S40F1020C7N consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the EP1S40F1020C7N. M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 318 MHz. The EP1S40F1020C7N is grouped into columns across the device in between certain LABs. M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits).

Parametrics

EP1S40F1020C7N absolute maximum ratings: (1)Supply voltage With respect to ground, VCCINT: –0.5 to 2.4V; (2)Supply voltage With respect to ground, VCCIO: –0.5 to 4.6V; (3)DC input voltage, VI: –0.5 to 4.6V; (4)DC output current, per pin, IOUT: –25 to 40mA; (5)Storage temperature No bias, TSTG: –65 to 150℃; (6)Junction temperature BGA packages under bias, TJ: 135℃.

Features

EP1S40F1020C7N features: (1)Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources; (2)TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers; (3)Up to 16 global clocks with 22 clocking resources per device region; (4)Support for numerous single-ended and differential I/O standards; (5)Differential on-chip termination support for LVDS; (6)Support for high-speed external memory, including zero bus turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM), and single data rate (SDR) SDRAM; (8)Support for 66-MHz PCI (64 and 32 bit) in -6 and faster speed-grade devices, support for 33-MHz PCI (64 and 32 bit) in -8 and faster speed-grade devices; (9)Support for 133-MHz PCI-X 1.0 in -5 speed-grade devices; (10)Support for 100-MHz PCI-X 1.0 in -6 and faster speed-grade devices; (11)Support for 66-MHz PCI-X 1.0 in -7 speed-grade devices; (12)Support for multiple intellectual property megafunctions from Altera MegaCore functions and Altera Megafunction Partners Program (AMPPSM) megafunctions; (13)Support for remote configuration updates.

Diagrams